The present disclosure relates to a memory apparatus in which a memory cell including a storage element capable of storing and retaining information based on a state of electric resistance.
Semiconductor non-volatile memories such as a flash memory are small in size and capable of retaining recorded data even when the power of the apparatus is turned off, and accordingly, the semiconductor non-volatile memories are widely used as recording mediums for recording moving images and sounds.
It is desired to increase recording capacity and increase recording density in non-volatile.
The non-volatile memories having larger recording capacity and higher recording density may include a non-volatile memory capable of multi-valued recording. That is, capable of storing data of 2 bits or more in one memory cell. The non-volatile memory capable of recording 2-bit data indicates a storage element forming a memory cell that can hold information in four recording states or levels.
Examples of a memory having such multi-valued technology include a flash memory or a resistance change type memory capable of recording information based on the change of a resistance value of a storage element.
The resistance change type memory that is capable of recording information by applying a voltage pulse to a storage element is disclosed in “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, written by W. W. Zhuang et al., Technical Digest “International Electron Devices Meeting”, 2002, page 193, for example. The resistance value of the storage element may be changed by changing the number of times to apply the voltage pulse to the storage element to realize multi-valued recording.
However, writing operation of a flash memory is performed by injecting electric charges stepwise into a terminal floating gate. If the flash memory is configured such that the flash memory may carry out multi-valued recording, longer time to realize multi-valued recording may be required as than when perfuming 1-bit recording (single value recording).
Further, when multi-valued recording is carried out using the resistance change type memory, there may also require longer time, because stepwise resistance change to realize multi-valued recording is controlled by varying the number of times to apply the voltage pulse to the terminal. Thus, increase an operation speed may also be difficult.
When recording information in the storage element capable of performing the multi-valued recording, a plurality of bits may be input and electric charges may be injected corresponding to a plurality of input bits or the voltage pulse may be applied the number of times. Thus, recording operations (electric charge injection or the number of times in applying the voltage pulse to the storage element) may preferably be performed corresponding to a relationship between a plurality of input bits and multi-valued information to be recorded may be performed using a simple circuit having excellent area efficiency.
Accordingly, a memory apparatus capable of carrying out multi-valued recording at high speed and including a driving circuit having a simple circuit with high area efficiency is desired.
Japanese Unexamined Patent Publication No. 2005-235360 discloses that a memory apparatus including a memory cell having a storage element and a circuit element such as a MIS (metal-insulator-semiconductor) transistor, and in which a resistance value of the storage element is controlled by controlling a voltage or current applied to the storage element or the circuit element so that multi-valued recording can be performed.
In the memory apparatus having this configuration, when “writing” is defined as an operation to change the resistance value of the storage element from high to low and “erasing” is defined as an operation to change the resistance value of the storage element from low to high, a resistance value obtained after writing (i.e., a state in which the resistance value is low) includes a plurality of levels so that multi-valued recording; that is, three or more values including a resistance value obtained after erasing (i.e., a state in which the resistance value is high) may be recorded.
However, in the memory apparatus having the above-mentioned configuration, when an erasing operation is carried out, the memory apparatus may provide routes for respective levels in order to shift the resistance value stored in the storage element from a plurality of levels of the resistance value obtained after erasing (e.g., three routes for three levels) to a high level so that erase characteristics in the respective routes may be different. Here, “erase characteristics” include a resistance value obtained after erasing, variability of the resistance value obtained after erasing, retention characteristics of recorded information (retention characteristics of resistance value) and the like.
If the resistance value obtained after erasing has large variability, when recorded information is read from the memory apparatus, recorded information cannot accurately be retrieved from the memory apparatus, thereby resulting in a read error.
If a voltage applied to the storage element to erase recorded information is not applied to all the corresponding routes, recorded information will fail to be erased.
Accordingly, it is desired that incompatibility of erase characteristics can be eliminated.